搜索资源列表
D
- 这是一个用VHDL实现一个D触发器的程序-This is a VHDL implementation of a D flip-flop process
simple_fm_receiver_latest.tar
- 用FPGA实现简单的FM接收机，d/a模块用扬声器-FPGA implementation using a simple FM receiver, d/a module with speaker
D
- 数字电子电路中的D触发器的VHDL的实现-Digital electronic circuits in the D trigger VHDL realization
VHDL
- eda开发中认识各种d触发器的功能程序-d triggers development of eda function program
VHDL-simple-examples
- 上传的几个VHDL程序：分别是各种功能计数器；使用列举类型的状态机，四D触发器，通用寄存器，伪随机比特发生器，简单的状态机。-Upload several VHDL program: are the various functions of the counter using the enumerated type state machine, four D flip-flop, the general-purpose registers, pseudo-random bit generato
csvd-d
- vhdl implementation of pong
TLC5510-VHDL
- 基于VHDL语言，实现对高速A/D器件TLC5510控制-Based on the VHDL language, to achieve high-speed A/D devices TLC5510 control
VHDL-book3
- D_flipflop：1位D触发器的设计 D_fllipflop_behav：4位D触发器的设计 reg1bit：1位寄存器设计 reg4bit：4位寄存器设计 shiftreg4：一般移位寄存器的设计 ring_shiftreg4：环型移位寄存器的设计 debounce4：消抖电路的设计 clock_pulse：时钟脉冲电路的设计 count3bit_gate：3位计数器的设计 count3bit_behav：3位计数器的设计 mo
vhdl
- library ieee use ieee.std_logic_1164.all entity decoder is port (clk:in std_logic clr:in std_logic data_in:in std_logic --待解码信元输入端； data_out:out std_logic) --解码信元输出端； end decoder architecture behave of decoder is component dff2
D-trigger
- FPGA/CPLD开发，基于VHDL语言的D触发器的实现-FPGA/CPLD development, based on VHDL implementation of the D flip-flop
VHDL-Code-For-BCD-To-Excess3--Code-Converter-By-D
- VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling-VHDL Code For BCD To Excess3 Code Converter By Data Flow Modelling
d_latch
- 使用VHDL编写的D触发器的简单程序，实现其功能-Simple and practical program written in VHDL D flip-flop
1.2Register-VHDL-and-testbench
- 用d type flip flop 改成的n bit 的寄存器，分别用到了同步和异步2种方式-With d type flip flop into the n bit registers were used in the synchronous and asynchronous 2 ways
pseudo-sequence-vhdl
- 常用的几种伪随机序列的仿真及性能分析，进而运用组合序列的思想，尝试不同的序列以不同组合方式生成的新的伪随机序列，并用FPGA分析其性能，得出组合序列的一般的规律，借此推导出了一种新的组合序列——异族Gold组合序列。-Through simulation and performance analysis of several commonly use¬ d pseudo-random sequence in the FPGA environment, use the ideas of c
VHDL-Language-Tutorial
- VHDL语言入门教程,详细介绍了VHDL的语法、如何使用及具体应用，适合研发人员入门及后期学习~-VHDL Language Tutorial, details the VHDL syntax, how to use and specific applications for R & D personnel entry and post-learning ~
ReadWrite-RAM-VHDL-source-code
- This page of VHDL source code covers read RAM and write to RAM vhdl code. RAM stands for Random Access memory.It is a form of data storage for various applications. 1K refers 10 lines used for Address bus (as 2^10=1024) 8 refers Data Bus
N-DtoA-VHDL-AMS
- 下面是一个混合信号的例子,是一个N位D/A转换器的VHDL-AMS描述-The following is an example of a mixed signal that is a N bit D/A converter described in VHDL-AMS
D-FLIP-FLOP
- vhdl programme of d flip flop
Compteur_VHDL
- VHDL code of a counter Code VHDL d un compteur
project.map
- D Flip Flop for Single Bit Store